Curriculum Vitae

Education

Northwestern University

Advisor: Peter Dinda

PhD Candidate in Computer Science (2019 - 2022)
Master of Science in Computer Science (2017 - 2019)

  • Murphy fellowship, 2017- 2018
  • Terminal Year fellowship 2021 - 2022

Rose-Hulman Institute of Technology

Bachelor of Science in Computer Engineering (2014 - 2017)

  • Graduated Cum Laude
  • Dean’s List 9/9 Quarters, Rose-Hulman Institute of Technology
  • True Merit Award, 2017, Alpha Tau Omega
  • Rose-Hulman Academic Merit Scholar

Publications

2022

CARAT CAKE: Replacing Paging via Compiler/Kernel Cooperation (to appear in ASPLOS '22) - PAPER

Brian Suchy, Souradip Ghosh, Drew Kersnar, Siyuan Chai, Aaron Nelson, Zhen Huang, Michael Cuevas, Alex Bernat, Gaurav Chaudhary, Nikos Hardavellas, Simone Campanoni, Peter Dinda

2020

CARAT: A Case for Virtual Memory through Compiler- And Runtime-based Address Translation (PLDI '20) - PAPER, TALK, POSTER

Brian Suchy, Simone Campanoni, Nikos Hardavellas, and Peter Dinda. 2020. CARAT: A Case for Virtual Memory through Compiler and Runtime-Based Address Translation. In Proceedings of the 41st ACM SIGPLAN International Conference on Programming Language Design and Implementation (PLDI ’20), June 15–20, 2020, London, UK. ACM, New York, NY, USA, 17 pages.

2019

Paths to Fast Thread Synchronization on the Node (HPDC '19) - PAPER

Conor Hetland, Georgios Tziantzioulis, Brian Suchy, Michael Leonard, Jin Han, John Albers, Nikos Hardavellas, and Peter Dinda. 2019. Paths to fast barrier synchronization on the node. In Proceedings of the 28th International Symposium on High-Performance Parallel and Distributed Computing (New York, NY, USA, 2019), HPDC ’19, ACM, pp. 109–120

Prospects for Functional Address Translation (MASCOTS '19) - PAPER

Conor Hetland, Georgios Tziantzioulis, Brian Suchy, Kyle Hale, Nikos Hardavellas, and Peter Dinda. Prospects for functional address translation. In 27th IEEE International Symposium on the Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (2019), MASCOTS ’19

Research Experience

(Current work available upon request)

CARAT CAKE: Replacing Paging via Compiler/Kernel Cooperation (ASPLOS 2022)

Northwestern University

  • Follow up to CARAT paper

  • Use the concepts of the CARAT paper, the Nautilus Aerokernel, and NOELLE, to create a full system implementation using CARAT as the underlying address space implementation.

CARAT: A Case for Virtual Memory through Compiler- And Runtime-based Address Translation (PLDI 2020)

Northwestern University

  • Used a compiler and runtime to build a dynamic, allocation level, memory mapping of a running program

  • Used runtime and compiler to perform memory management functions provided by virtual memory like movement and protection

  • Tested viability of using CARAT to act as a replacement of virtual memory to enable the removal of the TLB and paging.

Prospects for Functional Address Translation (MASCOTS 2019)

Northwestern University

  • Looked at alternative implementations to perform address translations in order to replace TLB

  • Investigated the feasbility of replacing TLBs with a perfect hash function generated by GPerf as well as minimal perfect hashing

  • Compared time and space complexity of new approach to traditional approach

Paths to Fast Barrier Synchronization on the Node (HPDC 2019)

Northwestern University

Building Blocks for Explicit Memory Management on Deep Memory Architectures

Argonne National Laboratory

  • Adding abstractions to complex memory systems to enable programmers to have explicit control over managing memory during execution

  • Testing the library on various benchmarks to compare performance improvement and simplicity of use over traditional, automated, approaches

  • Link to the Project

  • Creating report on the findings named "Building Blocks for Explicit Memory Management on Deep Memory Architectures"

Work Experience

Argonne National Laboratory

W. J. Cody Program Intern (2018)

  • Please see "Building Blocks for Explicit Memory Management on Deep Memory Architectures"

Texas Instruments

Automotive Applications Intern and Digital Systems Design Intern (2016 & 2017)

General Electric: Aviation Systems

Test Systems Engineering Intern (2015)

IT Consultant

Self Employed (2008 - Present)

Professional Affiliations

Institute of Electrical and Electronics Engineers (IEEE)


Eta Kappa Nu Honors Society (HKN)

Alpha Tau Omega National Fraternity (ATO)