Curriculum Vitae

Publications

2024

Program State Element Characterization (ASPLOS '24) -  PAPER
'Brian Tauro, Brian Suchy, Simone Campanoni, Peter Dinda, Kyle Hale

2023

Program State Element Characterization (CGO '23) -  PAPER
'Deiana, Enrico Armenio and Suchy, Brian and Wilkins, Michael and Homerding, Brian and McMichen, Tommy and Dunajewski, Katarzyna and Dinda, Peter and Hardavellas, Nikos and Campanoni, Simone

WARDen: Specializing Cache Coherence for High-Level Parallel Languages (CGO '23) -  PAPER
'Wilkins, Michael and Westrick, Sam and Kandiah, Vijay and Bernat, Alex and Suchy, Brian and Deiana, Enrico Armenio and Campanoni, Simone and Acar, Umut A. and Dinda, Peter and Hardavellas, Nikos

2022

CARAT CAKE: Replacing Paging via Compiler/Kernel Cooperation (ASPLOS '22) - PAPER

2020

CARAT: A Case for Virtual Memory through Compiler- And Runtime-based Address Translation (PLDI '20) - PAPER, TALK, POSTER

2019

Paths to Fast Thread Synchronization on the Node (HPDC '19) - PAPER

Prospects for Functional Address Translation (MASCOTS '19) - PAPER

Research Experience

(Current work available upon request)

CARAT CAKE: Replacing Paging via Compiler/Kernel Cooperation (ASPLOS 2022)

Northwestern University

• Follow up to CARAT paper 

• Use the concepts of the CARAT paper, the Nautilus Aerokernel, and NOELLE, to create a full system implementation using CARAT as the underlying address space implementation.

CARAT: A Case for Virtual Memory through Compiler- And Runtime-based Address Translation (PLDI 2020)

Northwestern University

• Used a compiler and runtime to build a dynamic, allocation level, memory mapping of a running program

• Used runtime and compiler to perform memory management functions provided by virtual memory like movement and protection

• Tested viability of using CARAT to act as a replacement of virtual memory to enable the removal of the TLB and paging.

Prospects for Functional Address Translation (MASCOTS 2019)

Northwestern University

• Looked at alternative implementations to perform address translations in order to replace TLB

• Investigated the feasbility of replacing TLBs with a perfect hash function generated by GPerf as well as minimal perfect hashing

• Compared time and space complexity of new approach to traditional approach

Paths to Fast Barrier Synchronization on the Node (HPDC 2019)

Northwestern University

• Researching the viability of alternatives to current barrier design and synchronization processes

• Created and compared an FPGA barrier to currently used software barrier solutions for micro-benchmarks, Streamcluster (Parsec 3.0), and parallel runtimes.

• Presented status update of project at GCASR '18 (Greater Chicago Area Systems Research Workshop)

Building Blocks for Explicit Memory Management on Deep Memory Architectures

Argonne National Laboratory

• Adding abstractions to complex memory systems to enable programmers to have explicit control over managing memory during execution

• Testing the library on various benchmarks to compare performance improvement and simplicity of use over traditional, automated, approaches

• Link to the Project

• Creating report on the findings named "Building Blocks for Explicit Memory Management on Deep Memory Architectures"

Work Experience

IT Consultant

Self Employed (2008 - Present)

Professional Affiliations