Curriculum Vitae

Education

Northwestern University

PhD Candidate in Computer Science

2019 - Present

Master of Science in Computer Science

2017 - 2019

Advisor: Peter Dinda

Rose-Hulman Institute of Technology

Bachelor of Science in Computer Engineering

2014 - 2017

Graduated Cum Laude

Publications

2020

CARAT: A Case for Virtual Memory through Compiler- And Runtime-based Address Translation (PLDI '20) - PAPER, TALK, POSTER

Brian Suchy, Simone Campanoni, Nikos Hardavellas, and Peter Dinda. 2020. CARAT: A Case for Virtual Memory through Compilerand Runtime-Based Address Translation. In Proceedings of the 41st ACM SIGPLAN International Conference on Programming Language Design and Implementation (PLDI ’20), June 15–20, 2020, London, UK. ACM, New York, NY, USA, 17 pages.

2019

Paths to Fast Thread Synchronization on the Node (HPDC '19) - PAPER

Conor Hetland, Georgios Tziantzioulis, Brian Suchy, Michael Leonard, Jin Han, John Albers, Nikos Hardavellas, and Peter Dinda. 2019. Paths to fast barrier synchronization on the node. In Proceedings of the 28th International Symposium on High-Performance Parallel and Distributed Computing (New York, NY, USA, 2019), HPDC ’19, ACM, pp. 109–120

Prospects for Functional Address Translation (MASCOTS '19) - PAPER

Conor Hetland, Georgios Tziantzioulis, Brian Suchy, Kyle Hale, Nikos Hardavellas, and Peter Dinda. Prospects for functional address translation. In 27th IEEE International Symposium on the Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (2019), MASCOTS ’19

Research Experience

CARAT: A Case for Virtual Memory through Compiler- And Runtime-based Address Translation (PLDI 2020)

Northwestern University

Used a compiler and runtime to build a dynamic, allocation level, memory mapping of a running program
Used runtime and compiler to perform memory management functions provided by virtual memory like movement and protection
Tested viability of using CARAT to act as a replacement of virtual memory to enable the removal of the TLB and paging.

Prospects for Functional Address Translation (MASCOTS 2019)

Northwestern University

Looked at alternative implementations to perform address translations in order to replace TLB
Investigated the feasbility of replacing TLBs with a perfect hash function generated by GPerf as well as minimal perfect hashing
Compared time and space complexity of new approach to traditional approach

Paths to Fast Barrier Synchronization on the Node (HPDC 2019)

Northwestern University

Researching the viability of alternatives to current barrier design and synchronization processes
Created and compared an FPGA barrier to currently used software barrier solutions for micro-benchmarks, Streamcluster (Parsec 3.0), and parallel runtimes.
Presented status update of project at GCASR '18 (Greater Chicago Area Systems Research Workshop)

Building Blocks for Explicit Memory Management on Deep Memory Architectures

Argonne National Laboratory

Adding abstractions to complex memory systems to enable programmers to have explicit control over managing memory during execution
Testing the library on various benchmarks to compare performance improvement and simplicity of use over traditional, automated, approaches
Link to the Project
Creating report on the findings named "Building Blocks for Explicit Memory Management on Deep Memory Architectures"